There has been known that liquid crystal display devices are widely used as a display element of such as televisions and graphic displays. Among them, a liquid crystal display device having a switching element such as a Thin Film Transistor (TFT hereinafter) in each pixel is particularly attracting attentions because it can provide high quality images without crosstalk among adjacent pixels, even if the number of pixel has been increased.
A main part of such a liquid crystal display device comprises a liquid crystal display panel 1001 and driving circuit section as shown in FIG. 7. In the liquid crystal panel, a liquid crystal layer is held between a pair of electrode substrates and polarizers are attached on each outer surface of the substrates.
One of the electrode substrates is a TFT-array substrate, which comprises a plurality of signal lines, S (1), S (2), . . . S (i), . . . S (N) and a plurality of scan signal lines, G (1), G (2), . . . G (j), . . . G (M) arranged in matrix formation on a transparent insulating substrate 1100 (made of glass or the like). At each intersection of a signal line and a scan signal line, there provided a switching element 1102 including a TFT, which is connected to a pixel electrode 1103. Then an alignment film covers over the substantially whole surface of the TFT-array substrate. In this way, the TFT-array is formed.
Another electrode substrate is a counter substrate, which comprises a counter electrode 1101 and an alignment film laminating in this order and covering over an entire surface of a transparent insulating substrate (made of glass or the like), similarly to the TFT-array substrate. The driving circuit section comprises a scan signal line driving circuit 1300 connected to every scan signal line aligned as explained above in the liquid crystal display panel, a signal line driving circuit 1200 connected to every signal line, and a counter electrode driving circuit COM connected to every counter electrode.
The scan signal line driving circuit (gate driver) 1300 comprises, as an example shown in FIG. 8, a shift register 1003a including cascade-connected an M number of flip-flops and selection switches 1003b each for turning ON and OFF in accordance with an output from the corresponding flip-flop.
An input terminal VD1 of each selection switch 1003b receives a potential Vgh for applying a gate ON voltage between source and gate. The gate ON voltage is sufficient for turning ON a TFT 1102. (referring FIG. 7) Another input terminal VD2 receives a potential Vgl for applying a gate OFF voltage between source and gate. The gate OFF voltage is sufficient for turning OFF the switch element 1102.
Accordingly, a data signal (GSP) is transmitted to flip-flops one after another and outputted to the selection switches 1003b respectively in accordance with a clock signal (GCK). In response to this, each selection switch 1003b outputs the potential Vgh for turning ON a TFT to a scan signal line 1105 for one selected scanning period, and then outputs the potential Vgl for turning off the TFT to the scan signal line 1105. As a result, the image signal supplied from the signal line driving circuit 1200 to each signal line 1104 (referring to FIG. 7) enables to write in each corresponding pixel.
FIG. 9 shows an equivalent circuit for one pixel P (i, j). The equivalent circuit includes a pixel capacitor C1c and an auxiliary capacitor Cs connected to a counter potential VCOM of the counter electrode driving circuit COM in parallel. In the FIG. 9, Cgd refers to a parasitic capacity between gate and drain in a TFT.
FIG. 10 is a waveform chart showing driving waveforms of a conventional liquid crystal display device. In the FIG. 10, Vg refers to a waveform of a scan signal line, Vs refers to a waveform of a signal line, and Vd refers to a drain wave.
The explanation of a conventional drive system is as follows with reference to FIG. 7, FIG. 9, and FIG. 10. It is widely known that liquid crystal display devices require an alternating current drive in order to prevent image deterioration and image sticking. The following explanation of a conventional drive system is also exemplified a frame inversion driving scheme, one kind of the alternating current drive schemes.
As shown in FIG. 10, when the electric potential Vgh is applied to a gate electrode g (i, j) of a TFT in one pixel P (i, j) from the scan signal line driving circuit 1300 in a first field (TF 1) (referring FIG. 7), the TFT turns ON. Then, an image signal voltage Vsp supplied from the signal line driving circuit 1200 is written in the pixel electrode through a source electrode and a drain electrode of the TFT. Then the pixel electrode preserves a pixel potential Vdp until the electric potential Vgh is applied in a second filed (TF 2). (referring FIG. 10) The counter electrode is set to a certain counter potential VCOM by the counter electrode driving circuit COM. Thus, the liquid crystal composition maintained in the pixel electrode and the counter electrode responds to a potential difference between the pixel potential Vdp and the counter potential VCOM, whereby an image is displayed.
In the same, when the electric potential Vgh is applied to the TFT gate electrode g (i, j) of the pixel P (i, j) from the scan signal line driving circuit 1300 in the second field (TF2) as shown in FIG. 10, the TFT turns ON. Then an image signal voltage Vsn supplied from the signal line driving circuit 1200 is written into a pixel electrode. Then, a pixel potential Vdn is maintained therein. The liquid crystal composition responds to a potential difference between the pixel potential Vdn and the counter potential VCOM, whereby, an image is displayed, and a liquid crystal alternating current drive is realized as well.
As shown in FIG. 9, a parasitic capacitor Cgd is naturally generated between the gate and drain of the TFT because of its structure. Therefore, when the potential Vgh drops, a level shift ΔVd occurs in a pixel potential Vd due to the parasitic capacitor Cgd. Where Vgl is a voltage when scanning signal is not scanned (a voltage when a TFT is OFF), a level shift ΔVd in a pixel potential Vd caused by a naturally generated parasitic capacitor Cgd is represented by the following formula:ΔVd=Cgd(Vgh−Vgl)/(C1c+Cs+Cgd).
This causes problems in images on a display such as flickers and image deteriorations, which is not preferable at all for the liquid crystal display devices pursuing higher definition and quality.
A conventional art has been proposed, in which a counter potential VCOM of a counter electrode is biased to reduce the amount of level shift ΔVd caused by the parasitic capacitor Cgd in advance.
In the conventional art, however, it is difficult to dispose a plurality of scan signal lines G (1), G (2), . . . G (j), . . . G (M) on a transparent (such as made of glass) insulating substrate 100 (as shown in FIG. 7) in an ideal wiring free from signal propagation delay. Thus, in the conventional art, the scan signal lines G are signal delay paths that have a certain signal propagation delay.
FIG. 11 shows a propagation equivalent circuit, for explanation on the signal propagation delay in a scan signal line G (j). In FIG. 11, rg 1, rg 2, rg 3, . . . rg N represent resistor components mainly caused by materials, width, and length of a wiring composing the scan signal line. Also, cg 1, cg 2, cg 3, . . . cg N represent a variety of parasitic capacities in capacity coupling relationship with the scan signal line structurally, such as a cross capacity generated by crossing over signal lines. Therefore, the scan signal line is a signal propagation delay path of distribution constant type.
FIG. 12 shows how rounding of a scan signal VG (j) supplied from the scan signal line driving circuit 1300 to a scan signal line proceeds inside the panel due to the mentioned signal propagation delay characteristic. A waveform Vg (l, j) in FIG. 12 has little rounding because it is a waveform close to g (l, j) that is located right after the output from the scan signal line driving circuit 1300. However, also in FIG. 12, a waveform Vg (N, j) that is located close to the end of the signal line g (N, j) has rounding due to the signal propagation delay characteristic of the scan signal line. Because of the rounding, a variation per unit time SyN is generated.
In addition, TFT is not a perfect ON and OFF switch, and it has a V-I characteristic (gate voltage-drain current characteristic) as shown in FIG. 13. In FIG. 13, the horizontal axis of the graph refers to a voltage applied to a TFT gate, and the vertical axis of the graph refers to a drain current. Normally, a scanning pulse comprises two electric potentials, a potential Vgh enough to turn ON the TFT and a potential Vgl enough to turn OFF the TFT. As shown in FIG. 13, there is a transitional TFT ON region (linier region), in a midway between VT (threshold of TFT) and Vgh.
Therefore, as shown in FIG. 12, in the pixel at g (l, j), which is located right after the output from the scan signal line driving circuit 1300, the fall of the scan signal from Vgh to Vgl is so quick that the feature in the linear region has no effect. The level shift ΔVd (1) generated at the pixel potential Vd (l, j) due to the mentioned parasitic capacity Cgd is approximately:ΔVd(1)=Cgd(Vgh−Vgl)/(C1c+Cs+Cgd)
However, at the pixel located close to the end of the scan signal line g (N, j), the fall of the scan signal has rounding. Therefore, during the transition from Vgh to around VT (threshold of TFT), the level shift caused by the parasitic capacitor Cgd does not occur in the pixel potential Vd because the TFT is ON due to the effect of the features in the linear region. During the transition from around VT (threshold of TFT) to Vgl, the level shift ΔVd (N) at the pixel potential Vd (N, j) occurs due to the parasitic capacitor Cgd. As a result, the level shift ΔVd (N) is:ΔVd(N)<Cgd(Vgh−Vgl)/(C1c+Cs+Cgd)Then, ΔVd (1)>ΔVd(N) is satisfied.
As explained above, the differentiation of the level shift ΔVd in the pixel potential Vd caused by the parasitic capacitor Cgd inside the panel is not uniform over the entire surface of the display and the differentiation is not ignorable in becoming higher definition and upsizing display. Accordingly, the conventional method of biasing the counter voltage leads to malfunctions such as flicker and image sticking caused by an application of DC component, because this method fails to cancel off the unevenness of the level shift over the entire surface of the display and drive each pixel in optimal alternating current.
As an invention to solve the malfunctions, there is a display device described in patent document 1. The explanation of the display device is as follows with reference to the accompanying drawings. FIG. 14 is a block diagram showing the structure of the scan signal line driving circuit 2001 of the display device. FIG. 15 (a) shows a waveform of a signal generated by the scan signal line driving circuit 2001 and FIG. 15 (b) shows a waveform of a signal supplied from the scan signal line driving circuit 2001.
As shown in FIG. 14, a plural of scan signal line driving circuits 2001 are disposed in one display device. The scan signal line driving circuit 2001 comprises an internal moderation section 2002 and a scan signal line driving section 2003.
The potential Vgh is applied to the internal modulation section 2002, then the internal modulation section 2002 modulates the potential Vgh and generates a driving signal VM having a waveform like reversed teeth of a saw as shown in FIG. 15 (a). The scan signal line driving section 2003 generates a scan signal VG shown in FIG. 15 (b) from the driving signal VM. The waveform of the scan signal VG rises vertically from the potential Vgl to the potential Vgh. After the potential Vgh for a certain period of time is maintained, the waveform of the scan signal VG falls with a linear slope, then fall substantially vertically to the potential Vgl. Because of the slope in the fall of the scan signal VG, the scan signal VG hardly has rounding. Then the effect of the characteristic in the linear region (shown in FIG. 13) is equalized between TFTs, one is located right after the output from the scan signal line driving circuit 1300 and another is located at the end of scan signal line. As a result, the level shift ΔVd generated in the pixel potential Vd due to the parasitic capacitor Cgd inside the panel is substantially equalized over the surface of the display.    Patent Document 1: Japanese Unexamined Patent Application (Translation of PCT Application) No. 10-504911